This invention relates to a semiconductor memory device and more particularly, to a dynamic random access memory (DRAM) device in which a constant reference electrical potential can be obtained regardless of the manufacturing processes of the device.
Since the advent of the 16 kbit DRAM, in a transistor cell DRAM, dummy cells each having a capacity one half that of the memory cell were used for setting the reference electrical potential. In this instance, it is so designed that the area of the capacitor in the dummy cell be one half that in the memory cell, as the process has been accomplished. Because the memory cell and the dummy cell differ in configuration, however, the effect of variations intrinsic to the manufacturing processes makes it difficult to always have the capacitance of the dummy cell be exactly one half that of the memory cell. As a result, the reference electrical potential obtained by reading the charge in the dummy cell has some variation. Consequently, the range of the operation margin of the sense circuit is narrowed, inviting a reduction in the yield of the whole semiconductor memory device in the final analysis.
The prior art device has such a problem. Thus, it is a hard way to try to attain a higher degree of integration.